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PCI Express 7.0 Spec Hits Draft 0.3, 512GBps Connectivity on Track For 2025 Release
(www.anandtech.com)
this post was submitted on 13 Jun 2023
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Technology
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Ultimately depends on how the motherboard manufacturers implement it and the choices they provide. If they were smart they wouldn't narrow lanes, but instead break up most of the higher speed lanes into multiple lower speed ones.
Just as an example, that x16 lane slot to the CPU, with PCIe-6.0 you could break it up into three 4.0x16 slots and four 4.0x4 NVME slots.
Granted, at PCIe-6.0 your probably well beyond the total bandwidth a normal user would need. At that point you hope as the technology matures so it can reduce costs by reducing how many lanes a CPU and motherboard need at all.
Ah ... I didn't realize "downscaling" (there's a better term I'm sure) at the motherboard level to older generations was a thing. Wait. Is that already a thing with some of the 5.0/4.0 boards?
Yes, that's what they have been doing for quite a while now.
The chipset splits a few PCIe lanes from the CPU into many PCIe lanes for lower speed devices to use. Of course those lanes all share the same bandwidth with each other and with the USB and SATA ports in the chipset.