2x Cortex X930 @ ~4 GHz.
6x Cortex A730 @ ~3.5 GHz.
TSMC N3P.
1x Cortex X925 (2 MB L2) @ 3.6 GHz.
3x Cortex X4 (1 MB L2) @ 3.3 GHz.
4x Cortex A720 (512 KB L2) @ 2.4 GHz.
TSMC N3E.
1x Cortex X4 (1 MB L2) @ 3.25 GHz.
3x Cortex X4 (512 KB L2) @ 2.8 GHz.
4x Cortex A720 (256 KB L2) @ 2.0 GHz.
TSMC N4P.
Cache sizes of 9500 CPU are unknown, but it can be expected to be similar or higher than 9400.
What is immediately noticeable is that 9500 changes to a 2+6 design from the 1+3+4 design of 9400. You might think they are simply copying the 2+6 design introduced by 8 Elite, but the reasons are quite sophisticated.
Cortex X930 and A730 are ARMv9.4 cores. So they cannot mixed and match with ARMv9.2 cores (X925, X4, A725, A720). Dimensity 9500 will also adopt SME, which necessitates that all the cores in the CPU should be of the X930/A730/A530 generation.
If Mediatek was to keep using the 1+3+4 design, they'll have to use 4 X930 cores and 4 A730 cores. X930 is huge (12 wide decoder), has high licensing cost, and it consumes a ton of power. So having 4 X930 cores in a smartphone SoC is unsustainable. This is why Mediatek opted for a 2+6 design.
Having 6 A730 cores is great for power efficiency (at the lower section of the curve), because they have less leakage than Cortex X cores. You can see this in Geekerwan's video on 8400, where it has even better power efficiency than 9400 and 8 Elite at the lower section of the power curve, thanks to the 8 A725 cores.