this post was submitted on 17 Feb 2024
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I am curious about why performance cores would go with a no-smt implementation; the die area improvements are obvious, but how are they going to spend that die area improvement to make up the performance gap?
AVX only really affects a small subset of applications, so I can't see that going too far.
A better branch predictor could be a boon, but given how good they are already I'm not sure how they could make up the 50% multi threaded loss.
Perhaps just cramming more physical cores together and a better cache sharing mechanism?
The multi thread performance would be handled by e cores. I guess the trade off for smt is no longer worth it with e cores in the picture.