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iPhone 16 Storage (lemmy.world)

submitted 1 month ago by [email protected] to c/[email protected]

57 comments fedilink hide all child comments

I know it's been a running joke for years now, but jesus christ the iPhones still start at 128GB and the regular 16 is still 60Hz and USB 2.0.

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[–] [email protected] 5 points 1 month ago* (last edited 1 month ago) (1 children)

Packaging flash storage onto the actual ~~SoC~~ SiP costs more than manufacturing the same amount of storage into an M.2 or external USB form factor, so that price can't be directly compared. They're making a big chunk of profit on storage upgrades, and on cloud subscriptions, but it's not exactly cheap to give everyone 1TB of storage at that base price.

[–] [email protected] 2 points 1 month ago (1 children)

That’s fascinating. My understanding was that flash storage is not physically integrated into the SoC but rather remains a separate ship that is sometimes stacked vertically.

[–] [email protected] 3 points 1 month ago (1 children)

You're right, it's not the same die, but the advanced packaging techniques that they keep improving (like the vertical stacking you mention) make for a much tighter set of specs for the raw flash storage silicon compared to what they might be putting in USB drives or NVMe sticks, in power consumption/temperature management, bus speeds/latency, form factor, etc.

So it'd be more accurate to describe it as a system on a package (SiP) rather than a system on a chip (SoC). Either way, that carries certain requirements that aren't present for a standalone storage package separately soldered onto the PCB, or even storage through some kind of non-soldered swappable interface.

[–] [email protected] 1 points 1 month ago (1 children)

Thanks! It’s nice to learn something new.

[–] [email protected] 2 points 1 month ago

Yeah, this advanced packaging stuff is pretty new, where they figured out how to make little chiplets but still put them onto the same package, connected by new tech that finally allows for high speed, low latency connections between chiplets (without causing dealbreaker temperature issues). That's opened up a lot of progress even as improving the circuits on the silicon itself has run into engineering challenges.

So while TSMC seemingly ahead of its competition on actually printing circuits on silicon with smaller and denser features, advanced packaging tech is going a long way in allowing companies to mix and match different pieces of silicon with different strengths and functionality (for a more cost effective end solution, and making better use of the nodes that aren't at the absolute bleeding edge).

Engineers are doing all sorts of cool stuff right now.