this post was submitted on 14 May 2024
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[–] [email protected] 9 points 5 months ago (15 children)

Well, do you have dedicated JSON hardware?

[–] [email protected] 2 points 5 months ago (1 children)
[–] [email protected] 1 points 5 months ago (3 children)

The R in ARM and RISC is a lie.

[–] [email protected] 1 points 5 months ago* (last edited 5 months ago)

The website title says "Arm Developer", not "ARM Developer", in a clearly non-acronym way so it's a guide for making prosthetic hardware. Of course you want a cyborg arm to parse JS natively, why else even get one?

[–] [email protected] 1 points 5 months ago

Lie starts with L, dummy

[–] [email protected] 1 points 5 months ago

Nope it's still a register-register op, that's very much load-store architecture.

It's reduced, not minimalist, otherwise every RISC CPU out there would only have one instruction like decrement and branch if nonzero. RISC-V would not have an extension mechanism. The instruction exists because it makes things faster because you don't have to do manual bit-fiddling over 10 instructions to achieve a thing already-existing ALU logic can do in a single cycle. A thing that isn't even javascript-specific (or terribly relevant to json), it's a specific float to int cast with specific rounding and overflow mode. Would it more palatable to your tastes if the CPU were to do macro-op fusion on 10(!) instructions to get the same result?

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